Classical semiconductor scaling, typically known as a device shrink, is currently supplemented by effective scaling, using techniques such as stress memorization. With circuits becoming smaller and faster, improvement in device drive current (Ion) is becoming more important. Drive current is closely related to gate length, gate capacitance, and carrier mobility. Stress memorization techniques are being used to speed carrier mobility in transistor channels, enabling higher drive currents.
Stress or strain in a device may have components in three directions, parallel to the metal-oxide-semiconductor (MOS) device channel length, parallel to the device channel width, and perpendicular to the channel plane. The strains parallel to the device channel length and width are called in-plane strains. Research has revealed that a bi-axial, in-plane tensile strain field can improve NMOS (n-channel MOS transistor) performance, and compressive strain parallel to channel length direction can improve PMOS (p-channel MOS transistor) device performance.
One way to develop strain is by using a graded SiGe epitaxy layer as a substrate on which a layer of relaxed SiGe is formed. A layer of silicon is formed on the relaxed SiGe layer. MOS devices are then formed on the silicon layer, which has inherent strain. Since the lattice constant of SiGe is larger than that of Si, the Si film is under biaxial tension and thus the carriers exhibit strain-enhanced mobility. The lattice spacing mismatch between the SiGe layer causes the underlying layer to develop an in-plane stress to match the lattice spacing. This additional processing may add cost to the semiconductor device manufacturing process.
Strain can also be applied by forming a strained capping layer, such as a barrier layer, on a MOS device. However, the barrier layer may not produce sufficient stress to produce the desired results. The conventional method of forming strained capping layers, suffers drawbacks, and the effect is limited by the properties of the capping layer. For example, the thickness of the strained capping layer is limited due to the subsequent gap filling difficulty caused by the thick capping layer. Therefore, the strain applied by the capping layer is limited. In addition, forming a strained capping layer that has customized strains for different devices, such as PMOS and NMOS devices, is particularly complex and costly.